Contador de 0000 - 9999, 9999 - 0000 VHDL Nexys 2

Codigo del modulo VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity q is
Port ( CLK_50Mhz,a,c,r,p : in STD_LOGIC;
an : out STD_LOGIC_VECTOR (3 downto 0);
indicador : inout STD_LOGIC;
Display : out STD_LOGIC_VECTOR (7 downto 0));
end q;
architecture Behavioral of q is
signal bcd :STD_LOGIC_VECTOR (3 DOWNTO 0);
signal bcd1 :STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000";
signal bcd2 :STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000";
signal bcd3 :STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000";
signal bcd4 :STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000";
signal temp :STD_LOGIC_VECTOR (19 DOWNTO 0) := "00000000000000000000";
signal temp1 : integer :=0;
signal sel :STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
begin
relomux: process (CLK_50Mhz)
begin
if CLK_50Mhz='1' and CLK_50Mhz'event then
temp <= temp + 1;
if temp = "00000000100000000000" then
if sel < "11" then
sel <= sel +1;
else
sel <= "00";
end if;
temp <="00000000000000000000";
end if;
end if;
end process;
PROCESO_CARGA_DESCARGA: process (CLK_50Mhz)
begin
if CLK_50Mhz='1' and CLK_50Mhz'event then
--CONT ASC
if c = '1' then
temp1 <= temp1 + 1;
if temp1 = 49999999 then
if bcd1 < "1001" then
bcd1 <= bcd1 +1;
indicador <= not indicador;
else
bcd1 <= "0000";
bcd2 <= bcd2 + 1;
if bcd2 < "1001" then
else
bcd2 <= "0000";
bcd3 <= bcd3 +1;
if bcd3 < "1001" then
else
bcd3 <= "0000";
bcd4 <= bcd4 +1;
if bcd4 < "1001" then
else
bcd4 <= "0000";
end if;
end if;
end if;
indicador <= not indicador;
end if;
temp1 <=0;
end if;
end if;
--CONT DES
if c = '0' then
temp1 <= temp1 + 1;
if temp1 = 49999999 then
if bcd1 > "0000" then
bcd1 <= bcd1 -1;
indicador <= not indicador;
else
bcd1 <= "1001";
bcd2 <= bcd2 - 1;
if bcd2 > "0000" then
else
bcd2 <= "1001";
bcd3 <= bcd3 -1;
if bcd3 > "0000" then
else
bcd3 <= "1001";
bcd4 <= bcd4 -1;
if bcd4 > "0000" then
else
bcd4 <= "1001";
end if;
end if;
end if;
indicador <= not indicador;
end if;
temp1 <=0;
end if;
end if;
--RESET
if r = '1' then
bcd1 <= "0000";
bcd2 <= "0000";
bcd3 <= "0000";
bcd4 <= "0000";
indicador <= '0';
end if;
--PARO + RESET
if p = '1' then
bcd1 <= bcd1;
bcd2 <= bcd2;
bcd3 <= bcd3;
bcd4 <= bcd4;
indicador <= '0';
if r = '1' then
bcd1 <= "0000";
bcd2 <= "0000";
bcd3 <= "0000";
bcd4 <= "0000";
indicador <= '0';
end if;
end if;
end if;
end process;
Multiplexor: process (sel,bcd1,bcd2,bcd3,bcd4)
begin
case sel is
when "00" => bcd <= bcd1; an<= "1110";
when "01" => bcd <= bcd2; an<= "1101";
when "10" => bcd <= bcd3; an<= "1011";
when "11" => bcd <= bcd4; an<= "0111";
when others => bcd <= "0000";
end case;
end process;
with bcd select
display <= "11111001" when "0001", --1
"10100100" when "0010", --2
"10110000" when "0011", --3
"10011001" when "0100", --4
"10010010" when "0101", --5
"10000010" when "0110", --6
"11111000" when "0111", --7
"10000000" when "1000", --8
"10010000" when "1001", --9
"11000000" when others; --0
end Behavioral;

Codigo para el UCF NEXYS 2

# PlanAhead Generated physical constraints
NET "CLK_50Mhz" LOC = B8;
NET "Display[0]" LOC = L18;
NET "Display[1]" LOC = F18;
NET "Display[2]" LOC = D17;
NET "Display[3]" LOC = D16;
NET "Display[4]" LOC = G14;
NET "Display[5]" LOC = J17;
NET "Display[6]" LOC = H14;
NET "Display[7]" LOC = C17;
NET "an[3]" LOC = F15;
NET "an[2]" LOC = C18;
NET "an[1]" LOC = H17;
NET "an[0]" LOC = F17;
NET "c" LOC = r17;
NET "indicador" LOC = r4;
NET "r" LOC = b18;
NET "p" LOC = g18;